1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory and a nonvolatile memory system using the nonvolatile semiconductor.
2. Description of the Related Art
An electrically programmable EEPROM (Electrically Erasable Programmable Read Only Memory) is traditionally known as one of the semiconductor memory devices. In particular, a NAND cell type EEPROM (a NAND type flash memory) comprised of blocks (NAND cell blocks) which connect a plurality of memory cells MTr in series has been paid attention to as a memory in which high integration and larger capacity may be expected compared to other memories. The conventionally used data program-and-erase operations of the NAND cell type EEPROM are as follows.
The program operation of the NAND type flash memory is mainly performed in order from the memory cell MTr which is farthest from the bit line BL. At first, when a data program operation is initiated, 0V (“0” data program) or a power-supply voltage Vcc (“1” data program) is applied to the bit lines corresponding to the program data, and a power-supply voltage Vcc is applied to the selection bit line BL side selection gate line. In this case, when the bit line BL is 0V, in the connected selection NAND cell block, the channel region within the NAND cell block is set to 0V via the selection gate transistor. When the bit line BL is the power-supply voltage Vcc, in the selection NAND cell block which is connected to this bit line BL, the channel region within the NAND cell block is charged to [Vcc-Vtsg] (here, Vtsg is a threshold voltage of the selection gate transistor) via the selection gate transistor, and afterwards becomes a floating state.
Next, the control gate line of the selection memory cell within the selection NAND cell block is set to Vpgm (for instance, about 20V, i.e., high voltage for programming) from 0V, and the control gate line of the non-selection memory cell within the selection NAND cell block is set to Vmg (for instance, about 10V: intermediate voltage) from 0V.
Here, when the bit line BL is 0V, in the NAND cell block which is connected to this bit line BL, the channel region within the NAND cell block is set to 0V, a large potential difference (for instance, about 20V) occurs between the gate (=Vpgm potential) and the channel region (=0V) of the selection memory cell within the selection NAND cell block, and electron injection occurs in the floating gate from the channel region. Thus, the threshold of the selection memory cell is shifted in a positive direction. This state is known as data “0”.
On the other hand, when the bit line BL is the power-supply voltage Vcc, in the selection NAND cell block which is connected to this bit line BL, because the channel region within the NAND cell block is in a floating state, the voltage of the control gate line increases (0V→Vpgm, Vmg) by the effects of capacity coupling between the control gate line and the channel region within the selection NAND cell block. Accompanied with this increase (step up) in voltage, the potential of the channel region is increased to Vmch (for instance, about 8V) from [Vcc-Vtsg], which maintains the control gate in a floating state. When this occurs, the potential difference between the gate (=Vpgm potential) and the channel region (=Vmch potential) of the selection memory cell within the selection NAND cell block is relatively small, about 12V and thus electron injection does not occur. Therefore, the threshold of the selection memory cell does not change and is maintained in a negative state. This state is known as data “1.”
A data erase operation of the NAND type flash memory is performed on all the memory cells MTr at once within the selection NAND cell block. That is, all control gates within the selection NAND cell block are set to 0V, the bit line BL, the common source line SOURCE, the control gates in the non-selection NAND cell block and all the selection gates are set to a floating state, and a high voltage of about 20V, for instance, is applied to the p-type well (or the p-type substrate). Thereby, electrons of the floating gate are released into the p-type well (or the p-type substrate) in all the memory cells MTr in the selection NAND cell block, and the threshold voltage is shifted in a negative direction. Thus, in the NAND type flash memory, the data erase operation is performed in block units.
The data readout operation of the NAND type flash memory is performed by setting the control data of the selection memory cell to 0V and detecting whether or not current flows in the selection memory cell as a voltage (for instance, 5V) provided from stress at the time of the readout operation of the control gate and the selection gate of the non-selection memory cell.
However, the following problems have been identified in the conventional program method (See Japanese Laid Open Patent 07-169284 and G. J. Hemink et al., Symposium on VLSI Technology Digest of Technical Papers, 1995, pp. 129-130 for reference).
At the time of programming, the shape of a program pulse is preferred to be “an ideal trapezoid-shaped waveform”, but it is difficult to install a program pulse generation circuit which generates “an ideal trapezoid waveform” within the same memory cell array. In the conventional program method, the pulse waveform is set to a “step-shaped waveform.” Therefore, there was a problem in which programming efficiency deteriorated compared to the ideal trapezoid-shaped waveform.
In addition, while it is possible to change the shape of the program pulse to appear more similar to “the ideal trapezoid-shaped waveform” by making an interval of the program pulse of the step-shaped waveform smaller, there was, however, a problem in which the number of verify operations increases and as a consequence, program time and erase time increases.